(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for fabricating a new dynamic random access memory (DRAM) cell. The method utilizes a buried N.sup.+ doped region in a silicon substrate which is removed by selective etching to form a cavity. The cavity wall is then coated with a dielectric layer and filled with a polysilicon to form a horizontally extending buried reservoir storage capacitor which increases capacitance.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are used for storing digital information on arrays of memory cells in the form of charge stored on a capacitor. Each memory cell consists of a single access transistor and a single storage capacitor. The access transistors are usually N-channel field effect transistors (FETs) and the FET gate electrodes are electrically connected by word lines to the peripheral address circuits. The storage capacitors are formed either by etching trenches in the substrate in each cell areas, commonly referred to as trench capacitors, or are formed over the access transistors in the cell areas by depositing and patterning conducting layers over the access transistors, and are commonly referred to as stacked capacitors. The capacitors make electrical contact to one of the two source/drain areas (node contact) of each FET (access transistor), while bit lines make electrical contact to the other source/drain area of each FET. Read/write circuits, on the periphery of the DRAM chip, are used to store binary data by charging or discharging the storage capacitor via the bit lines, and the binary data is read (or sensed) by peripheral sense amplifiers, also via the bit lines. However, each capacitor must lie within an area about the size of the cell area in order to accommodate all the capacitors in the large array of cells used on the DRAM device.
It is becoming increasingly difficult to fabricate more memory cells on a DRAM device, while limiting the overall DRAM device area to a practical size without decreasing the cell area. For example, after the year 2000 the number of memory cells is expected to reach multiple Gigabits. Further, as the cell area decreases, the available area for the storage capacitor in each cell also decreases. This makes it difficult to maintain sufficient capacitance for storing charge to provide the necessary signal-to-noise ratios. Also the refresh cycle time, necessary to maintain the required charge on these capacitors, also decreases, resulting in DRAM devices with reduced performance (speed).
One method in the semiconductor industry of overcoming the above problems is to form DRAM devices having stacked capacitors. These types of capacitors extend vertically upward (z-direction) over the access transistor and can be made with increased area (A) in the z-direction while maintaining or minimizing the area along the substrate surface (along the x-y directions). The two basic types of stacked capacitors for the DRAM cells of the prior art are the Capacitor Under Bit line (CUB) structure and the Capacitor Over Bit line (COB). However, in either the CUB or COB structure, the bit line and capacitor must share the same space on the memory cell area. More specifically, in the CUB structure the bit line contact must be formed in the same plane as the storage capacitor, and in the COB structure the node contact must be formed in the same plane as the bit line. For DRAM cells having submicrometer dimensions, it is becoming more difficult to maintain adequate separation between the bit line contact and the storage capacitor for the CUB structure, and between the node contact and bit line for the COB structure. This makes it difficult to fabricate reliable DRAM devices having stacked capacitors.
Also the topography on the DRAM device having stacked capacitors can be quite rough, and leveling and planarizing techniques are employed to provide a planar surface on which submicrometer structures (e.g., bit lines) can be reliably formed. These planar surfaces are needed to expose the high-resolution, distortion-free photoresist images (patterns) because of the shallow depth of focus (DOF) required for high-resolution exposures. Also planar surfaces are necessary to avoid residue (rails, fences, etc.) at steep steps when the next levels of conducting layers are anisotropically plasma etched. Another problem is the high aspect ratio (height/width) of the bit line contact holes that can result in high contact resistance.
An alternative method for making an array of DRAM cells is by forming deep trench capacitors in the silicon substrate. By forming the storage capacitors in a trench etched in the silicon substrate, it is possible to leave the surface on the substrate free for the bit lines, thereby providing adequate separation between bit line and storage capacitor. This also allows memory cells to be built with smaller surface areas for future high-density DRAM arrays.
One conventional trench capacitor DRAM cell is described by Ghandhi in "VLSI Fabrication Principles" second edition, pages 741-742, published by John Wiley & Sons, Inc., New York. In this method (FIG. 11.26(a)) a deep trench having vertical walls is etched in the a P.sup.+ substrate having a P epitaxy layer. A thin insulating layer is formed on the trench sidewall, and a P.sup.+ polysilicon fills the trench to form the storage capacitor. An N-well and a field oxide (FOX) are formed next to define and electrically isolate adjacent device areas. Word lines (which concurrently form the P-channel FET gate electrodes of the access transistors) are formed over the device areas adjacent to the trench capacitors. To increase capacitance two or more trench capacitors can be used, as shown in the DRAM cell design of FIG. 11.26(b). However, this requires additional substrate surface area and limits cell density.
There are several other process limitations for making the current trench capacitor DRAM cell. For example, to achieve sufficient storage capacitance as the cell area decreases, the capacitor trench must be etched very deep (e.g., having aspect ratios of 20 to 40) and is difficult to etch and fill with the polysilicon. For future ULSI requirements, the DRAM trench aspect ratio is expected to increase further. Another shortcoming of this conventional trench capacitor process is that the trench cannot be extended in the cell area under the FET to take advantage of the increased capacitor area derived therefrom.
Another approach is to extend trench capacitors under the FET (to save cell space) as described in Wolf, Vol. 2, pages 609, and depicted in FIGS. 8-24 and 8-25 on page 611. The structure is a Self-aligned Epitaxy Over Trench (SEOT) cell which uses a double epitaxy process. After forming a storage electrode (P.sup.+ polysilicon node electrode) in a trench, that is completely isolated from the P.sup.+ substrate, a selective epitaxy layer is laterally grown to form a single-crystal P.sup.- silicon over the SiO.sub.2 -isolated trench capacitor. However, the epitaxial growth is stopped before the epitaxy has completely grown over the trench to form a self-aligned window (opening). The SiO.sub.2 in the window is etched to expose the P.sup.+ polysilicon in the trench, and a second P.sup.- epitaxial layer is grown to form a pyramidal polysilicon in the window as the capacitor node contact for a P-channel FET memory cell. However, the multiple epitaxy is not cost effective; controlling the window size on 256 Mbit or 1 gigabit DRAM devices would be difficult to control; and the use of a P.sup.+ storage electrode in a P.sup.+ substrate is also more susceptible to leakage currents through the high-k dielectric.
Still other approaches to making trench capacitors with increased surface area are described in the prior art. For example Ohtsuki, U.S. Pat. No. 5,629,226, teaches a method for forming a buried (trench) capacitor in which an N.sup.+ implant is formed at the bottom of the trench and annealed to diffuse into the silicon substrate. The annealed N.sup.+ silicon is then selectively etched to increase the trench area and therefore the capacitance. Another approach for making deep trench capacitors for DRAM cells is described by Alsmeier et al., U.S. Pat. No. 5,627,092, in which vertical deep trench capacitors are made in a Silicon On Insulator (SOI). Another approach for increasing the capacitance of a vertical trench capacitor is taught by D. J. Chin et al. in U.S. Pat. No. 5,432,365. A high dopant concentration by ion implant is formed in the substrate to form one of the capacitor electrodes. This apparently further reduces the depletion layer in the substrate at the capacitor during charge storage and increases capacitance. Still another method is described by McElroy, U.S. Pat. No. 4,896,293, in which the access transistor is formed in one sidewall of the capacitor trench in which the FET source makes contact to the capacitor node plate while the FET drain is formed in the top surface of the substrate. This reduces surface area and increases cell density, but also requires a deeper trench to increase capacitance.
There is still a strong need in the semiconductor industry to further improve upon fabricating trench storage capacitors for DRAM cells with increased capacitance while minimizing the depth of the capacitor trench (decreased aspect ratio), and with improved reliability and manufacturing cost performance.